Ultra-large scale integrated circuits technology has been driven by the scaling down of CMOS device to improve the performance, as well as to reduce the cost. However, when the device dimension entered the sub-100 nm regime, the impact of short channel effects such as drain-induced barrier lowering (DIBL), shift of threshold voltage, off-state leakage current increasing and sub-threshold slope (SS) degradation are becoming more and more severe, which restricts the device dimension from further downscaling. Besides adopting novel device structures and new materials, the impact of the short channel effects of the MOSFET can be reduced by changing the operating mechanism of field effect transistor, for example, by employing a tunneling field-effect transistor (TFET).
The TFET is essentially a gate controlled reverse-biased PIN diode. FIG. 1 shows a sectional view of a typical TFET along the channel direction. As different from a conventional MOSFET, doping types of source and drain regions of the TFET are different, wherein the drain end is N+-doped and a positive bias voltage is applied thereto during operation, whereas the source end is P+-doped and a negative bias voltage is applied thereto during operation. The operating principle of the TFET will be briefly described as follows by taking an N-type TFET as an example. In off-state, as shown in FIG. 2, the barrier layer between the source and the drain is very thick, thus the electron tunneling can not occur. At this time, the device is a reverse-biased PIN junction, hence the source-drain punch through effect in the conventional CMOS device can not happen, and the leakage current is small. Therefore, TFET is applicable for low power consumption applications. In on-state, as shown in FIG. 3, a positive voltage is applied to the gate and the electric potential in the channel region is lowered, thus the thickness of barrier layer between the source region and the channel region is reduced, therefore, electrons can tunnel through the source end to the channel region and then drift to the drain end. In comparison with the conventional MOSFET, the TFET can obtain a smaller sub-threshold slope (SS), which makes it applicable for low power consumption applications. The reasons are as follows: the source injection of the conventional MOSFET is based on a diffusing-drifting mechanism, and a Fermi-Dirac distribution of carriers makes the SS proportional to the thermoelectric potential kT/q, wherein a minimum possible value of the SS at room temperature is 60 mV/dec; while the source injection of the TFET is based on a tunneling mechanism, thus the SS no longer relies on the restriction of the thermoelectric potential kT/q. It has been indicated by a theoretical calculation that the SS of the TFET can be smaller than 60 mv/dec (See Q. Zhang. et al. IEEE Electron Device Lett., vol. 27, pp. 297-300, 2006.). It has been verified by W. Choi, et al. for the first time, through experiments, that a sub-threshold slope smaller than 60 mv/dec can be obtained for a Si TFET at room temperature (See W. Choi, et al. IEEE Electron Device Lett., vol. 28, pp. 743-745, 2007.). Moreover, the TFET can exhibit better short channel immunity than the conventional MOSFET due to the change of carrier injection mechanism in the source region, which facilitates reducing the cost by improving the integration density.
Two times of photolithography process are needed to form the source and the drain regions of TFET due to the different doping types of the source and drain regions. Thus it is very difficult to fabricate TFET based on the self-aligned planar fabrication process of conventional MOSFET. Due to the influence of the alignment deviation, requirements on the photolithography process will be very high when a planar TFET is fabricated by the conventional non-self-aligned process. Particularly, when the device has a short channel length, the unstability of device characteristics caused by the alignment deviation of the photolithography becomes more severe. In order to overcome the alignment problem of TFET, a TFET having a vertical structure can be fabricated, as reported in the document C. Sandow, et al. Solid-State Electronics, vol. 53, pp. 1126-1129, 2009 and in the document Z. X. Chen, et al. IEEE Electron Device Lett., vol. 30, pp. 754-756, JULY 2009. Furthermore, a method for fabricating a TFET based on a self-aligned sidewall process has also reported in document W. Choi, et al. IEEE Electron Device Lett., vol. 28, pp. 743-745, August 2007. However, for a TFET fabricated by the above methods, overlap between the gate region and the source (or drain) region is very large, which may increase the parasitic capacitance and gate leakage; moreover, the compatibility between the TFET having a vertical structure and the existing planar ultra-large scale integrated circuit is poor, which is unfavorable for an integration of the TFET and the traditional planar MOSFET. Therefore, it is necessary to develop a method for self-alignedly fabricating a TFET based on the traditional CMOS planar process.